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Rambus released CXL 2.0 and PCIe controller with zero latency IDE.

Rambus released CXL 2.0: Rambus Inc, a premium chip and silicon IP provider recently announced Compute Express Link (CXL) 2.0 and PCI Express (PCIe) 5.0 controllers which are now available with integrated Integrity and Data Encryption (IDE) modules. It will provide the needed speed and security to solve the bandwidth bottleneck problem faced in data centres. 

“Successful enablement of CXL use models in data-intensive applications, such as memory sharing between processors and attached AI accelerators, requires security at ultra-low latency,” said Sean Fan, chief operating officer at Rambus. “Delivering controllers with zero-latency security is a testament of our ability to accelerate the development of CXL solutions through the recent acquisition of PLDA, and showcases our unique position to provide integrated interface and security IP solutions.” Said Sean Fan, The Chief Operating Officer at Rambus. 

CXL solutions

These two IDE models employ a 256-bit AES-GCM (Advanced Encryption Standard, Galois/Counter Mode) symmetric-key cryptographic block cypher which helped chip designers and security architects to ensure confidentiality, integrity and reply protection for traffic that travels over CXL and PCIe links. 

There are some key features of their new IDE models – 

  • IDE security with zero latency for CXl.mem and CXL.cache.
  • Minimize the safety, financial, and brand reputation risks of a security breach.
  •  The pre-integrated IDE module will reduce implementation risks and speed time-to-market. 

For more information, you can check out the Press-release at Rambus’s website, Here.

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